A typical frequency mixer implemented in a radio transceiver comprises an oscillator signal generation circuit (phase locked loop (PLL), for example) to provide an oscillator signal having a first frequency and one or more frequency dividers dividing the frequency of the oscillator signal output from the oscillator signal generation circuit to a desired frequency (or frequencies). The output signal of a selected frequency divider is then used for up-converting a transmission signal to a desired radio frequency and/or down-converting a reception signal from the radio frequency to a baseband or to an intermediate frequency band.
In current radio systems, the frequency divider used in the oscillator signal generation circuitry after a voltage-controlled oscillator (VCO) is designed to operate at certain frequency ranges and amplitudes specified by the system or by the properties of the VCO. The plans of the future multi-standard radio systems increase the operational frequency range of the divider and, thereby, requirements of the frequency divider. A conventional solution to ensure an adequate performance of the frequency divider is to increase the VCO output power, but that consumes power and is, therefore, not a preferable solution. Requirements for the operational frequency ranges of the frequency dividers may range within several GHz. The operation of the frequency divider on any given frequency within this range becomes a challenge, because maximum swing and minimum noise are required of the divider within the whole specified frequency range.